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cortex m hardfault decoder

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ARM Cortex-M HardFault Decoder

When your processor enters HardFault_Handler, you usually do not know why. To find out, you must read the value of the CFSR (Configurable Fault Status Register) at address 0xE000ED28. Enter its HEX value below, and the analyzer will decode the hardware fault flags!

System Control Block Fault Registers (SCB)

Contains MMFSR, BFSR, and UFSR packed into 32 bits.
Status of the master HardFault exception.

UsageFault (UFSR)

  • [0] UNDEFINSTR - Undefined Instruction
  • [1] INVSTATE - Invalid State (e.g. attempting to use ARM instruction in Thumb state)
  • [2] INVPC - Invalid PC Load EXC_RETURN
  • [3] NOCP - No Coprocessor (No FPU but float instruction used)
  • [8] UNALIGNED - Unaligned Memory Access
  • [9] DIVBYZERO - Division by zero!

BusFault (BFSR)

  • [0] IBUSERR - Instruction Bus Error
  • [1] PRECISERR - Precise Data Bus Error (We know the exact fault address!)
  • [2] IMPRECISERR - Imprecise Data Bus Error (Buffered write failed in the background)
  • [3] UNSTKERR - Error unstacking for EXC_RETURN
  • [4] STKERR - Error stacking for exception entry
  • [7] BFARVALID - BusFault Address Register (BFAR) is valid! Read 0xE000ED38.

MemManage (MMFSR)

  • [0] IACCVIOL - Instruction access violation (MPU Error)
  • [1] DACCVIOL - Data access violation (RAM/Peripheral access denied by MPU)
  • [3] MUNSTKERR - MemManage fault on unstacking
  • [4] MSTKERR - MemManage fault on stacking
  • [7] MMARVALID - MMFAR address register is valid! Read 0xE000ED34.

HardFault (HFSR)

  • [30] FORCED - Forced HardFault (escalated from another fault e.g. Usage/Bus)
  • [31] DEBUGEVT - HardFault triggered by Debug event

MODULE UNDER CONSTRUCTION

EXPECTED DEPLOYMENT: Q4 2026